1. Field of the Invention
The present invention relates to logic simulation apparatuses and circuit simulation apparatuses for verifying circuit operation characteristics of logic circuits.
2. Description of the Background Art
FIG. 21 is a block diagram showing structure of a conventional logic simulation apparatus having a function of calculating signal propagation delay time.
As shown in the figure, a layout pattern data storing portion 1 provides a data extracting portion 2 with layout pattern data D1 defining layout pattern of a logic circuit which is an objective of the logic simulation.
The data extracting portion 2 extracts circuit data D2 including circuit connection data defining relation of connections among elements constituting the logic circuit, circuit constant data of the elements and interconnection dimension data including information on dimensions of diffusion regions for elements and information on dimensions of interconnections among the elements from the layout pattern data D1, and outputs the same to a gain coefficient calculating portion 5 and a parasitic capacitance calculating portion 6.
A process parameter storing portion 3 outputs process parameters D3 required in a process of manufacturing the logic circuit to the gain coefficient calculating portion 5 and the parasitic capacitance calculation portion 6.
The gain coefficient calculating portion 5 calculates coefficient of gain for each element of the logic circuit on the basis of the circuit constant data in the circuit data D2 and the process parameters D3 and outputs the same to a propagation delay calculating portion 10.
The parasitic capacitance calculating portion 6 calculates parasitic capacitance associated with each interconnection on the basis of the circuit constant data, the dimension information about diffusion regions, the interconnection dimension data in the circuit data D2 and the process parameters D3, and outputs the same to the propagation delay calculating portion 10.
A power-supply voltage storing portion 4 outputs power-supply information D4 including voltage values and internal resistance value of power-supply operating the logic circuit to the propagation delay calculating portion 10.
The propagation delay calculating portion 10 calculates signal propagation delay time required for each element to propagate a logic signal on the basis of the gain coefficient obtained from the gain coefficient calculating portion 5, the parasitic capacitance obtained from the parasitic capacitance calculating portion 6 and the power-supply information D4, and outputs the same to a delay value providing portion 11.
The delay value providing portion 11 provides the elements on the circuit connection data with the signal propagation delay time obtained from the propagation delay calculating portion 10 and outputs the same to a logic simulation performing portion 12.
The logic simulation performing portion 12 performs the logic simulation on the basis of the circuit connection data in which the elements are provided with the signal propagation delay time in the delay value providing portion 11.
The operation of the logic simulation apparatus shown in FIG. 21 will be described below.
First, the data extracting portion 2 extracts from the layout pattern data D1 the circuit data D2 involving the circuit connection data, the circuit constant data for elements and the interconnection dimension data, and outputs the same to the gain coefficient calculating portion 5 and the parasitic capacitance calculating portion 6.
Then the gain coefficient calculating portion 5 calculates gain coefficients for respective elements on the basis of the circuit constant data (channel lengths and channel widths of transistors, etc.) in the circuit data D2 and the process parameters D3 (dielectric constants, film thicknesses of gate oxide films, etc.) and outputs the same to the propagation delay calculating portion 10.
At the same time, the parasitic capacitance calculating portion 6 calculates interconnection parasitic capacitance associated with each interconnection on the basis of the circuit constant data (the channel lengths, channel widths of transistors, etc.), the dimension information of diffusion regions, the interconnection dimension data in the circuit data D2 and the process parameters D3 (dielectric constants and thicknesses of insulating films formed right below interconnection regions, etc.) and outputs the same to the propagation delay calculating portion 10.
Then, the propagation delay calculating portion 10 calculates signal propagation delay time TD for each element on the basis of the gain coefficient and the interconnection parasitic capacitance and outputs the same to the delay value providing portion 11.
Next, the delay value providing portion 11 provides the signal propagation delay time TD to each element in the circuit connection data and outputs the circuit connection data provided with the signal propagation delay time TD to the logic simulation performing portion 12.
Then, by the logic simulation performed on the basis of the circuit connection data provided with the signal propagation delay time TD, the logic simulation is enabled in consideration of the signal propagation delay time of elements in the logic circuit objective to the simulation.
The conventional logic simulation apparatus configured as described above had a problem that the reliability in the signal propagation delay time is low because the signal propagation delay time for respective elements calculated in the propagation delay calculating portion 10 is based only on the coefficients of gain and the interconnection parasitic capacitances.